Silicon-based Terahertz systems is a field that is only about a decade old. In this time, we have seen a phenomenal growth of silicon systems operating at THz frequencies for a wide range of applications in sensing, imaging and communication. It can be argued that both the ‘THz gap’ and the ‘technology and applications gap’ is closing in meaningful ways in the THz range. Technologies beyond 100 GHz focusing on sensing, imaging and wireless back-haul links are getting attractive as we enter into a new area of highly dense network of autonomous systems requiring ultra-high speed and reliable links.

In order to move beyond this inflection point as Moore’s law continue to slow, I will discuss why we need to look beyond the classical ‘device’-level metrics of efficiency and sensitivity of THz sources and detectors towards holistic ‘system’ level properties such as scalability and programmability. Such properties are critically important for applications in sensing and imaging, as evidenced across sensor fusion technologies across mmWave, IR and optical frequencies. The ultimate programmability in THz sources and sensors is one that can synthesize or receive THz fields with arbitrary configuration and spectrum. In this talk, I will highlight approaches that cut across electromagnetics, circuits, systems and signal processing, to allow for such reconfigurability in THz signal synthesis and sensing, yet realized with devices that are themselves not very efficient. Particularly, we will demonstrate approaches to THz CMOS sensors reconfigurable across the three field properties of spectrum (100 GHz-1000 GHz), beam pattern and polarization, programmable THz metasurfaces with CMOS tiling, and enabling dynamic spectrum shaping and physically secure sub-THz links. In the end, I will comment on what could be the major directions for the field in the coming decade.

Hello IEEE Central Coast Students,

This Video Essay Contest is for Central Coast Students Only. Please see below for contest information.

Prizes: First to third place, 0, 0, 0.

Judges: Members of the Executive Committee, IEEE Central Coast Section

Motivation: We are all experiencing difficulties, as we work to fulfill our educational missions and goals, while facing a vicious pandemic. Our task may have gotten harder by political unrest unfolding in the United States, which may signal at least a few weeks of turmoil. Here is something to keep us busy and connected in these challenging times.

Contest description: IEEE CCS is asking its student members to share their experiences over the past year in a video-essay, no longer than 3 minutes. You can speak about your experience, include project demos, and anything else you would like to share. There are many resources on-line to help you prepare your video-essay. Here is an example:

https://ecu.au.libguides.com/video-essay/how-to-do-a-video-essay

SIGN UP for the CONTEST below at REGISTER NOW. A link to the Video Submission Site will be sent to you after you register.

Best regards,

Ruth Franklin IEEE Central Coast Chair

If you are considering making a career change, this webinar will cover practical and successful strategies that we suggest should be taken in the very early stages of the process. We will share easy-to-use methods and tools that will help you gain a deeper understanding of your strengths, gaps, opportunities, and challenges and how these can be used to launch a successful career transition. Think of this as a pre-planning exercise BEFORE you start thinking about writing a resume or conducting a job search.

Companion e-book
This session's presenter, Dr. Bob Danielle, authored an e-book on this subject (published by IEEE-USA in February of 2021).

• Click here to get your copy of "Career Transitioning 101 – Book 1: First Steps" 
  (Free to IEEE members, [vtools-xml.php] url[asc/6].99 for non-members).
  
  

Storage connects to systems thru layers with interfaces between the layers that have evolved over time – smaller size, lower cost and higher performance.  Early on “dumb” interfaces evolved in the market from the wide interfaces of dominant mainframe and minicomputer interfaces, e.g., DEC RP0x, SMD, etc.  Over time the interfaces became smarter, serial and sponsored by industry consortia (e.g., SCSI, SATA, NVMe), while at the same time function moved around in the various layers (e.g.  RAID, Caching, etc.)

Four industry participants will share with you their experiences in making storage work with computers.

Women in Engineering read 6 books a year. Each title is given a two-month period in which to complete the manuscript. The WIE members meet online monthly to discuss and enjoy each other's perspectives. This book club event will be in collaboration with the Women Who Code Book Club. 

IEEE Seattle Section Excom meeting with a chapter and society chairs. 

It can be difficult to find a computer exactly the way that one wants or needs just sitting on the shelf in a store. Some companies offer custom made ones but with a price to match. Additionally, no one source has all of the things that one would want. Quality becomes another issue as most people shop with price as a major controlling factor so companies are parsimonious in procuring the components.

Dr Morantz has combined his Electrical Engineering, Computer Science, Mathematics, and good common sense to build an 8-core hyperthreaded monster computer with strong performance and reliability while working with a financial budget to fits his own needs and desires.

This presentation covers this project from design phase to completion. This whole project took several months and has been very rewarding, both in having the computer that he needs and wanted, and in being a learning process. Much knowledge and experience was gained in the process. Dr Morantz will go through the steps explaining what he did and why.

Please note that this talk is presented by our Vice-Chair Brad Morantz, but is hosted by IEEE Foothill Section Computer Society

Superconducting qubits are a leading candidate for constructing a large-scale quantum processor due to their lithographic scalability and relatively long coherence times. 3D qubit packaging, enabling the integration of more chips with greater functionality, higher I/O counts, and smaller pad pitches –- while maintaining qubit coherence –- is critical for scalable computing architecture. In this talk, I will present a microbump-based assembly approach to produce three-tier stacks with a qubit chip on the top, superconducting multi-chip-module (SMCM) on the bottom, and an interposer chip with superconducting through-silicon vias (TSVs) in the middle. I will discuss our work developing a double bump-bonding process to create the qubit-interposer-SMCM stack, focusing on electrical characterization, alignment accuracy, spacing and co-planarity.

Circuits and Systems Society (CASS) of the IEEE Santa Clara Valley Section

6:55 - 7:00 PM Intro 7:00 - 7:50 PM Lecture7:50 - 8:00 PM Q&A/Adjourn

The electronic components are increasing in automotive applications replacing earlier mechanical and hydraulics solutions. With proper protection and diagnostics, we can ensure that these electronic components (power semiconductors/transistors) perform the expected function and achieve fail silent (fault tolerant) operation by sensing the fault and adapting its behavior. They also incorporate advanced and robust diagnostic circuits that provideinformation apriori for safety to the drivers/passengers in the cars about the load conditions, faults etc. Such components are referred to as the Smart Power Circuits. Their designs are not much different from the conventional analog circuits used in consumer electronics topology wise. However, they have to handle a wide range of input voltage (5V to 40V) and wide range of currents (30mA to 4A). There are additional system requirements and design implementation challenges that have to be considered when defining and implementing such circuits. This seminar/tutorial introduces the State-of-the-Art requirements of automotive ICs, design techniques, R-L-C type of loads, thermal simulations, reliability and explains the various Gate Drivers like the high side driver, low side driver configurable high side/low side drivers. Power supply sequencing, level shifters, charge pump, voltage-current selector circuits will be presented. High voltage, negative voltage tolerant switches for diagnostics and impact of on chip parasitic bipolar transistors in automotive applications are discussed.

Dr. –Ing Sri Navaneeth Easwaran, Senior Member IEEE, received his Bachelor's (1998, Bharathidasan University), Master's (2006, University Twente) degrees in Electrical Engineering and Dr. –Ing. degree from University of ErlangenNuremberg in 2017. He worked at SPIC Electronics, STMicroelectronics, Philips Semiconductors between 1998 and 2006. From 2006 he is with Texas Instruments (TI) where he was the design lead for airbag squib driver ICs. He has also designed high voltage and -40V tolerant circuits for automotive ICs. He is an IET Fellow (since Feb 2021) and a TI Senior Member Technical Staff. He has 20+ granted patents and 15 publications. He has offered tutorials on Automotive design at IEEE Conferences.

Amit Jha is inviting you to a scheduled Zoom meeting.

Topic: Amit Jha's Zoom Meeting

Time: May 13, 2021 07:00 PM Pacific Time (US and Canada)

Join Zoom Meeting

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Passcode: 315340

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We are continueing our speaker series with Shawn Duncan, VP – Cox. 

Register to hear Dr. Cynthia Furse, IEEE APS Distinguished Lecturer, talk about the history and future of implantable antennas!

Virtual Event Details

Software and Systems Engineering share the tasks of planning and managing their activities. This talk will describe the use of Causal Analysis to better understand how to estimate the cost of development/engineering which is in turn used in the planning and management of the work. While this talk addresses a particular type of engineering data, i.e. for engineering effort and related parameters, it is also meant to encourage the audience to apply the techniques to their own data.

This talk will cover the topic in four parts:
1. An introduction to causal analysis
2. A live demonstration of the Tetrad causal analysis tool
3. An introduction to the sources of the data we analyzed: the calibration data sets for COCOMO II and COSYSMO 3.0.
4. Application of causal analysis to the datasets, including the need for weak signal analysis and the generation of estimating equations. 

About the Speakers 

Jim Alstad, Ph.D 
 
Dr Jim Alstad received his PhD from USC under Dr Barry Boehm in 2018; his thesis topic was "COSYSMO 3.0: An Extended, Unified Cost Estimating Model for Systems Engineering". Previously, Jim had a 32-year career in software engineering at Hughes Aircraft and Boeing Satellite Systems. At Boeing Jim worked on satellite flight software on a variety of systems, including leading the Wideband Global SATCOM flight software team. He was an Associate Technical Fellow at Boeing. On the side, Jim taught courses at USC in various capacities for 13 years. He holds a patent on a satellite algorithm, “Fast Pair Catalog Access”. Next year, Jim will have been a member of ACM for 50 years.

Anandi Hira, Ph.D. 
@Tecolote Research Inc.

Anandi Hira is a Cost Analyst at Tecolote Research Inc, and has received her PhD in software cost estimation under Dr. Barry Boehm at University of Southern California (USC). For her research, she collected data and calibrated the COCOMO® II model to include functional size metrics. Her research interests include software metrics and its application to project management, software cost estimation, and software process improvement.

Zoom Webinar Instructions for first timers

This will be a ZOOM Webinar. Instructions:
1) Register usinng the External Event link below.
2) Upon completion, and on the same page as the registration, you will get a link to the meeting. [You can also add it to your calendar.]
3) Click on this link to open the webinar.

IEEE Solid-State Circuits Society Utah Chapter Spring 2021 Conference

Our understanding of the classical reliability concepts of security and adequacy is increasingly being challenged by: (a) growing shares of inverter-based resources and variable renewable energy technologies that call for new operation and planning approaches, particularly to deal with decreasing levels of inertia and system strength, larger reserve requirements, and increasing volumes of distributed energy resources that are not “visible” to the system operator; and (b) the more frequent occurrence of extreme, high-impact low-probability events (e.g., driven by climate change), with potentially catastrophic impacts.

In this IEEE PES Distinguished Lecture we will discuss how there is a need for introducing new analysis and modelling frameworks to deal with the increasing fragility of low-carbon grids and exposure to extreme events. The key desirable features of such frameworks will be presented for both operation and planning and from both technical and economic/commercial perspectives, along with metrics, methodologies and modelling tools that can help make future systems more secure, reliable and resilient.

The key question that will be asked is whether the grid should be made “stronger” (e.g., through component hardening), “bigger” (more redundant, through investment in new transmission/generation asset) or “smarter” (through new technologies and operational practices).

Besides different examples taken from the speaker’s several international projects in the area, the South Australia “Black System” event of September 2016, the Australian system separation event of August 2018, the UK demand disconnection event of August 2019, and the Texas power crisis of February 2021 will be taken as “textbook” case studies to practically illustrate some of the general concepts presented.

SCV WIE May 2021 ExCom

This webinar series will address the status of Digital Transformation in several areas (both as geography—North and Latin America, Europe, Far East Asia—and as market segments such as healthcare, manufacturing, retail, education). In addition, they will cover the expected evolution considering the impact of the pandemic and the recovery effort put in place by several Governments, including EU and US initiatives.

 In particular, the ongoing evolution of Industry 4.0 with the Gaia-X initiative in Europe will be addressed. This initiative, although fostered by EU, is already involving 200+ industries from all over the world, comprised by major US players in the Information Technology sector.

The Importance of Solar Resource Assessment and Monitoring in PV Power Plant Performance

The Product Safety Engineering Society meeting have presentations on regulatory safety, EMC and environmental requirement for electronic equipment

Circuits and Systems Society (CASS) of the IEEE Santa Clara Valley Section

6:55 - 7:00 PM Intro 7:00 - 7:50 PM Lecture7:50 - 8:00 PM Q&A/Adjourn

This work presents the implementation of the digital read-out architecture of a System-On-Chip (SoC) ASIC optimized for Time Projection Chamber (TPC) detectors used in neutrino science. The CRYO ASIC works at cryogenic temperatures and performs signal pre-amplification, waveform digitization and channel multiplexing with minimum number of I/Os. The digital back end is optimized to work with cryogenic liquids (LXe, 160K and LAr, 87K) providing data throughput up to 1 Gbps and can be programmed to maintain signal integrity up to 25m cable length. Implemented in 130nm CMOS process, the back-end architecture consists of a digital multiplexer, a custom 12b/14b encoder, a data serializer, and LVDS (Low-Voltage Differential Signaling) drivers with pre-emphasis enhancing techniques. The simulated output jitter of transmitter is 29.3ps, peak-to-peak (0.15UI) driving a 25m cable at 1Gbps data rate.

Aseem Gupta received his M.S degree in Electrical and Computer Engineering from Stony Brook University (SUNY), New York in 2015. He is currently a Staff Electronic Engineer at Stanford Linear Accelerator Center (SLAC) Laboratory, Instrumentation Division, Stanford University. He was also a Staff Research Associate at Brookhaven National Laboratory, NY from 2015-2017, where he worked on development of read-out logic for triggering the digital L0 buffer for ATLAS (A toroidal Large Hadron Collider Apparatus) experiment at CERN, Geneva. He is currently focused on development of a waveform digitizer ASIC operating at cryogenic temperatures for neutrino detection in Time Projection Chamber (TPC) experiments such as Deep Underground Neutrino Experiment (DUNE- 87K) and next Enriched Xenon Observatory (nEXO- 113K). His research interests are in high-speed LVDS driver, cable measurements, integrated circuits, and design of back-end architecture with Digital-on-Top methodology in mostly analog ASICs. He has authored/co-authored in various conference publications. He is an active IEEE member.

Amit Jha is inviting you to a scheduled Zoom meeting.

Topic: Amit Jha's Zoom Meeting

Time: May 27, 2021 07:00 PM Pacific Time (US and Canada)

Join Zoom Meeting

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Meeting ID: 899 1283 4102

Passcode: 526734

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Dial by your location

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+1 253 215 8782 US (Tacoma)

+1 346 248 7799 US (Houston)

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+1 301 715 8592 US (Washington DC)

Meeting ID: 899 1283 4102

Passcode: 526734

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All admissions free. Suggested donations:

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